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low-power direct digital modulation frequency synthesizer preliminary datasheet v1.2 PS2500 2.2 ghz fractional-n frequency synthesizer - 1 - features product description philsar semiconductor inc. 146 colonnade road s. nepean, ontario, canada k2e 7y1 tel: 613-274-0922 fax: 613-274-0915 www.philsar.com pmp-001-ds2 v1.2 the PS2500 direct digital modulation fractional-n frequency synthesizer provides ultra-fine frequency resolution, fast switching speed, and low phase-noise performance. this synthesizer is a key building block in designing high-performance narrowband and multi-band radio systems that require low power and fine step size. the ultra-fine step size of less than 100 hz allows this synthesizer to be used in very narrowband wireless applications. with proper temperature sensing or through control channels, the synthesizer?s fine step size can compensate for crystal oscillator or if filter drift. as a result, crystal oscillators or crystals can replace temperature-compensated or ovenized crystal oscillators, reducing parts count and associated component cost. the PS2500?s fine step size can also be used for doppler shift corrections. the PS2500 has a phase noise floor of -92 dbc/hz up to 2.2 ghz operation. this is permitted by the on-chip low noise prescalers and low divide ratios provided by the ic?s high fractionality. reference crystals or oscillators up to 50 mhz can be used with the PS2500. the crystal frequency is divided down by independent programmable dividers (1 to 32) for the main and auxiliary synthesizers. the phase detectors can operate at a maximum speed of 25 mhz, permitting better phase noise due to the lower division value. with a high reference frequency, the loop bandwidths can also be increased. larger loop bandwidths improve the settling times and reduce in-band phase noise. typical switching times of less than 100 m s can thus be achieved with a 10 mhz reference. the PS2500?s lower in-band phase noise also permits the use of lower cost voltage controlled oscillators (vcos) in customer applications. the PS2500 has a frequency power steering tm circuit (patent pending), which assists the loop filter to steer the vco when the frequency is too fast or too slow. in this configuration, acquisition times of up to five times faster than conventional phase/frequency detectors can be achieved. the unit operates with a 3-wire, high-speed serial interface. a combination of a large bandwidth, fine resolution, and the 3-wire, high-speed serial interface allows for a direct phase and frequency modulation of the vco. this supports any constant envelope and continuous phase modulation which means any analog fm or digital fm. this capability can eliminate the need for i & q dacs, quadrature upconverters, and if filters from the transmitter portion of the radio system. ? 2.2 ghz maximum operating frequency ? 500 mhz maximum auxiliary synthesizer ? ultra-small step size 100 hz or less ? high-reference frequency enables larger loop bandwidth pll ? fast switching speed ? phase-noise to -92 dbc/hz inside the loop filter bandwidth ? spurious -70 dbc/hz inside the loop filter bandwidth ? software programmable power-down modes ? high-speed serial interface ? 3-wire programming ? programmable division ratios on reference frequency ? phase detectors with programmable gain provide a programmable loop bandwidth ? frequency power steering tm speeds up acquisition 5x with same loop bandwidth ? on-chip crystal oscillator ? frequency adjust for temperature compensation ? direct digital modulation ? 3 volt operation ? 5 volt output to loop filter ? 28-pin ep-tssop package
PS2500 2.2 ghz fractional-n frequency synthesizer - 2 - philsar semiconductor inc. 146 colonnade road s. nepean, ontario, canada k2e 7y1 tel: 613-274-0922 fax: 613-274-0915 www.philsar.com pmp-001-ds2 v1.2 benefits the philsar PS2500 provides has the following benefits: ? small step size allows for higher internal reference frequency which permits a lower multiplication ratio improving phase noise. ? lower phase noise permits the use of a wider loop filter bandwidth, which in turn yields a faster frequency switching and acquisition time. ? small step size allows flexibility in choosing a reference crystal or oscillator frequency, as very narrow channel spacing can be supported. ? the on-chip oscillator permits use of a crystal instead of a crystal oscillator lowering the system cost. ? programmable phase detector gain allows for variable loop filer bandwidths. frequency switching and acquisition times can be improved by opening up the bandwidth, and subsequently lower phase noise contribution can be achieved by narrowing down the loop filter bandwidth after phase lock. ? programmable power-down modes optimize power management. ? individually configurable main and auxiliary synthesizers as integer-n, allowing a reduction in power consumption. ? configurable resolution of the main ds modulator from 18 to 10 bits, allowing further reduction in power consumption.
PS2500 2.2 ghz fractional-n frequency synthesizer - 3 - philsar semiconductor inc. 146 colonnade road s. nepean, ontario, canada k2e 7y1 tel: 613-274-0922 fax: 613-274-0915 www.philsar.com pmp-001-ds2 v1.2 figure 1: PS2500 block diagram product description serial interface the serial interface is a versatile 3-wire interface, clock (serial clock), data (serial input) and /cs (chip select). it enables the PS2500 to operate in a system where one or multiple masters and slaves are present. to perform a loop-back test at start-up and to check the integrity of the board and processor, the serial data can be fed back to the master device (for example, mcu/mpu) through a programmable multiplexer. this facilitates hardware and software debugging. for more information, see ? serial interface ? on page5. registers there are ten 16-bit registers in the PS2500. for more information, see ? registers ? on page19 and ? register descriptions ? on page19. main and auxiliary ds modulators the PS2500 uses a proprietary (patent pending) configurable 10-bit or 18-bit ds modulator for the main synthesizer and 10-bit ds modulator for the auxiliary synthesizer to provide fractionality. modul.data main ds main div. modul.ctl ref. div synthctl aux.div. aux. ds registers serial interface ds 18-bit modulation unit main prescaler main divider main phase/freq. reference frequency fractional unit detector and charge pump oscillator auxiliary phase/freq. detector and charge pump reference frequency dividers ds 10-bit auxiliary divider fractional unit auxiliary prescaler data clock /cs f vco_main /f vco_main f vco_aux /f vco_ aux f ref_main f ref_aux cp o ut_aux ld/ps aux cp o ut_main ld/ps main lock detection or power steering lock detection or power steering f ref mux_out mux f pd_main f pd_aux mod_in
PS2500 2.2 ghz fractional-n frequency synthesizer - 4 - philsar semiconductor inc. 146 colonnade road s. nepean, ontario, canada k2e 7y1 tel: 613-274-0922 fax: 613-274-0915 www.philsar.com pmp-001-ds2 v1.2 main and auxiliary fractional units the PS2500 provides fractionality through the use of main and auxiliary ds modulators. the output from the main and auxiliary modulators are combined with the main and auxiliary divider ratios through their respective fractional units. vco prescalers the vco prescalers provide low-noise signal conditioning of the vco signals. they are used to translate from an off-chip single-ended or differential signal to an on-chip differential ecl/cml signal. the PS2500 has independent main and auxiliary vco prescalers. main and auxiliary vco dividers the PS2500 provides programmable dividers that control the ecl/cml prescalers and supply the required signals to the charge pump phase detectors. programmable divide ratios ranging from 38 to 537 are possible in fractional-n mode and from 32 to 543 in integer-n mode. reference frequency oscillator the PS2500 has a self-contained low-noise crystal oscillator. this crystal oscillator is followed by the clock generation circuitry that generates the required clock for the programmable reference frequency dividers. reference frequency dividers the crystal oscillator signal can be divided by a ratio of 1 to 32 to create the reference frequencies for the phase detectors. the PS2500 has both a main and an auxiliary frequency synthesizer and provides independently configurable dividers of the crystal oscillator frequency for both the main and auxiliary phase detectors. the divide ratios can be programmed through the reference frequency dividers register. note: the divided crystal oscillator frequencies (which are the internal reference frequencies) f ref_main and f ref_aux are referred to as the reference frequencies throughout this document. phase detectors and charge pumps the PS2500 uses a separate charge pump phase detector (patent pending), for each synthesizer which provides a programmable gain, kd, from 20 to 160 m a/radian in steps of approximately 5 m a/radian. phase detector gains are programmable through the control register. frequency steering when programmed for power steering tm (patent pending), the PS2500 has a frequency power steering circuit, which assists the loop filter to steer the vco, through the ld/ps pin. in this configuration, the ld/ps pin can provide for more rapid acquisition (approximately five times faster than conventional phase/frequency detectors). when programmed for lock detection, internal frequency steering is implemented and provides frequency acquisition times comparable to conventional phase/frequency detector.
PS2500 2.2 ghz fractional-n frequency synthesizer - 5 - philsar semiconductor inc. 146 colonnade road s. nepean, ontario, canada k2e 7y1 tel: 613-274-0922 fax: 613-274-0915 www.philsar.com pmp-001-ds2 v1.2 lock detection when programmed for lock detection, the PS2500 provides on the ld/ps pin, an active low pulsing open collector output to indicate the out-of-lock condition. when locked, the ld/ps pin is tri-stated (high impedance). power down the PS2500 supports a number of power-down modes through its serial interface. for more information, see ? general synthesizer registers ? on page22. operation this section describes the operation of the PS2500. the serial interface is described first, followed by information on how to obtain values for the divide ratio registers. serial interface the serial interface of the PS2500 consists of three pins: clock , data and /cs . data transfers are controlled by the clock signal which synchronizes and samples the information on the two serial data lines ( data and /cs ). the bits on the data pin are shifted into a temporary register on the rising edge of clock . the /cs (chip select) line allows individual selection of slave devices on the same bus. the following diagram functionally depicts how a serial transfer takes place. figure 2: serial transfer timing diagram a serial transfer is initiated when a microcontroller or microprocessor forces the /cs line to a low state. this is immediately followed by an address/data stream being presented to the data pin that coincides with the rising edges of the clock presented on the clk line. each rising edge of the clk signal shifts in one bit of data on the data line into the shift-register. at the same time, one bit of data is being shifted out for the mux_out pin (if the serial bit stream is selected) at each falling edge of clk . to load any of the synthesizer registers, 16 bits of address/data have to be presented to the data line with the data lsb last while /cs is low. if /cs is low for more than 16 clock cycles, only the last address/data bits are used for loading the synthesizer registers. if the /cs line is brought to a high state before the thirteenth clock edge on clk , the bit stream is assumed to be modulation data samples. in this case, it is assumed that no address bits are present and that all the bits in the stream should be loaded into the modulation data register clock /cs data a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 xxx x a3 last
PS2500 2.2 ghz fractional-n frequency synthesizer - 6 - philsar semiconductor inc. 146 colonnade road s. nepean, ontario, canada k2e 7y1 tel: 613-274-0922 fax: 613-274-0915 www.philsar.com pmp-001-ds2 v1.2 synthesizer register programming in the following equations, fractional-n applications the desired division ratio for the main and auxiliary synthesizer is given by: n fractional = f vco / f div_ref where n fractional must be between 37.5 and 537.5 for the auxiliary. the value to be programmed in the main or auxiliary divider register is given by: n reg = round 1 [n fractional ] - 32 when in fractional mode, allowed values for n reg are from 6 to 505 inclusive. the value to be programmed in the main or auxiliary dividend register(s) is given by: dividend = round [divider x (n fractional - n reg - 32)] where the divider is either 1024 in 10-bit mode or 262144 in 18-bit mode. therefore, the dividend is a signed binary value either 10 or 18 bits long. n fractional desired vco division ratio in fractional-n applications. this number is a real number and can be interpreted as the reference frequency (f ref ) multiplying factor such that the resulting frequency is equal to the desired vco frequency. n integer desired vco division ratio in integer-n applications. this number is an integer and can be interpreted as the reference frequency (f ref ) multiplying factor such that the resulting frequency is equal to the desired vco frequency. n reg 9-bit unsigned input value to the divider ranging from 0 to 511(integer-n mode) and from 6 to 505 (fractional-n mode) divider 262144 when the ds modulator is in 18-bit mode, 1024 when the ds is in 10-bit mode dividend when in 18-bit mode, 18-bit signed input value to the ds modulator, ranging from -131072 to +131071 providing 262144 steps, each of f div_ref / 2 18 (hz). or when in 10-bit mode, 10-bit signed input value to the ds modulator, ranging from -512 to +511 providing 1024 steps, each of f div_ref / 2 10 hz. f vco desired vco frequency (either f vco_main or f vco_aux ). f div_ref divided reference frequency presented to the phase detector (either f ref_main or f ref_aux ). 1. where the round function rounds the number to the nearest integer.
PS2500 2.2 ghz fractional-n frequency synthesizer - 7 - philsar semiconductor inc. 146 colonnade road s. nepean, ontario, canada k2e 7y1 tel: 613-274-0922 fax: 613-274-0915 www.philsar.com pmp-001-ds2 v1.2 note: because of the high fractionality of the PS2500, there is no practical need for any integer relationship between the reference frequency and the channel spacing or desired vco frequencies. fractional-n example case 1: to achieve a desired frequency f vco_main of 902.4530 mhz using crystal frequency of 40 mhz with operation of the synthesizer in 18-bit mode. since the maximum internal reference frequency f div_ref is 25 mhz, the crystal frequency is divided by 2 to obtain a f div_ref of 20 mhz 1 . therefore, using: n fractional = f vco / f div_ref = 902.4530 / 20 = 45.12265 the value to be programmed in the main divider register is: nreg = round [nfractional] - 32 = round[45.12265] - 32 = 74 - 32 = 13 = 0 0000 1101(binary) with the modulator in 18-bit mode, the value to be programmed in the main dividend registers is: dividend = round (divider x (n fractional - n reg - 32)) = round (262144 x (45.12265 - 13 - 32)) = round (262144 x (0.12265)) = round (32151.9616) = 32152 (decimal) = 00 0111 1101 1001 1000 (binary) where 00 0111 1101 is loaded in the main dividend msb register and 1001 1000 is loaded in the main dividend lsb register . summarizing, ? main divider register = 0 0000 1101 ? main dividend lsb register = 1001 1000 ? main dividend msb register = 00 0111 1101 1. the frequency step size for this case is 20 mhz divided by 2 18 giving 76.3 hz .
PS2500 2.2 ghz fractional-n frequency synthesizer - 8 - philsar semiconductor inc. 146 colonnade road s. nepean, ontario, canada k2e 7y1 tel: 613-274-0922 fax: 613-274-0915 www.philsar.com pmp-001-ds2 v1.2 ? the resulting main vco frequency is 902.453 ? step size is 76.3 hz case 2: assuming a desired frequency f vco_main of 917.7786 mhz and a crystal frequency of 19.2 mhz with operation of the synthesizer in 10-bit mode. since the maximum internal reference frequency f div_ref is 25 mhz, the crystal frequency does not require the internal division to be greater than 1, giving us a f div_ref of 19.2 mhz 1 . therefore, using: n fractional = f vco_main / f div_ref = 917.7786 x 19.2 = 47.80139 the value to be programmed in the main divider register is: n reg = round [n fractional ] - 32 = round [47.80139] - 32 = 48 - 32 = 16 = 0 0001 0000 (binary) with the modulator in 10-bit mode, the value to be programmed in the main dividend registers is: dividend = round (divider x (nfractional - nreg - 32)) = round (1024 x (47.80139 - 16 - 32)) = round (1024 x (-0.19861)) = round (-203.38133) = -203 (decimal) = 11 0011 0101 (binary) where 11 0011 0101 is loaded in the main dividend msb register . summarizing, ? main divider register = 0 0001 0000 ? main dividend msb register =11 0011 0101 ? the resulting vco frequency is 917.7938 mhz ? step size is 18.75 khz 1. the frequency step size for this case is 19.2 mhz divided by 2 10 giving 18.75 khz.
PS2500 2.2 ghz fractional-n frequency synthesizer - 9 - philsar semiconductor inc. 146 colonnade road s. nepean, ontario, canada k2e 7y1 tel: 613-274-0922 fax: 613-274-0915 www.philsar.com pmp-001-ds2 v1.2 integer-n applications the desired division ratio for the main or auxiliary synthesizer is given by: n integer = f vco_main / f div_ref where n integer is an integer number from 32 and 543 for both the main and auxiliary synthesizers. the value to be programmed in the main or auxiliary divider register is given by: n reg = n integer - 32 when in integer mode, allowed values for n reg are from 0 and 511 for both the main and auxiliary synthesizers. note: as with all integer-n synthesizers, the minimum step size is related to the crystal frequency and reference frequency division ratio. integer-n example case 1: to achieve a desired frequency f vco_aux of 400 mhz using a crystal frequency of 16 mhz. since the minimum divide ratio is 32, the reference frequency must be a maximum of 12.5 mhz. choosing a reference frequency divide ratio of 2 provides us with a reference frequency f div_ref of 8 mhz. therefore, using: n integer = f vco_aux / f div_ref = 400 / 8 = 50 the value to be programmed in the auxiliary divider register is: n reg = n integer - 32 = 50 - 32 = 18 = 0 0001 0010 (binary) summarizing, ? auxiliary divider register = 0 0001 0010 register loading order in applications where the main synthesizer is in 18-bit mode, the main dividend msb register holds the 10 msbs of the dividend and the main dividend lsb register holds the 8 lsbs of the dividend . the order in which the registers controlling the main synthesizer?s divide ratio are to be loaded is: ? main divider register ? main dividend lsb register
PS2500 2.2 ghz fractional-n frequency synthesizer - 10 - philsar semiconductor inc. 146 colonnade road s. nepean, ontario, canada k2e 7y1 tel: 613-274-0922 fax: 613-274-0915 www.philsar.com pmp-001-ds2 v1.2 ? main dividend msb register (at which point the new divide ratio takes effect). in applications where the main synthesizer is in 10-bit mode, the main dividend msb register holds the 10 bits of the dividend . the order in which the registers controlling the main synthesizer?s divide ratio are to be loaded is: ? main divider register ? main dividend msb register (at which point the new divide ratio takes effect). for the auxiliary synthesizer, the auxiliary dividend register holds the 10 bits of the dividend . the order in which the registers controlling the auxiliary synthesizer?s divide ratio is to be loaded is: ? auxiliary divider register ? auxiliary dividend register (at which point the new divide ratio takes effect). note: when in integer mode, the new divide ratios take effect as soon as the main or auxiliary divider register is loaded. direct digital modulation the PS2500?s high fractionality and small step size permit the user to tune to practically any frequency in the vco?s operating range. this frequency tuning permits direct digital modulation by programming the different desired frequencies at precise instants. typically, the channel frequency is selected through the main divider and dividend register and the instantaneous frequency offset from the carrier is entered through the modulation data register. write access to the modulation data register can be performed three ways: normal register write a normal 16-bit serial interface write to the modulation data register at address hex9 where /cs is 16 clock cycles wide and modulation data is presented on the data pin. the content of the modulation data register is passed to the modulation unit at the next falling edge of the divided main vco frequency (f pd_main ). short /cs through data pin (no address bits required) a shortened serial interface write where /cs is from 2 to 12 clock cycles wide and modulation data (2 to 12 bits) is presented on the data pin. the data is the default pin for entering modulation data directly in modulation data register with shortened /cs strobes. this method of data entry eliminates the register address overhead on the serial interface. all serial interface bits are re-synchronized internally at the reference oscillator frequency. the content of the modulation data register is passed to the modulation unit at the next falling edge of the divided main vco frequency (f pd_main ). short /cs through mod_in pin (no address bits required)
PS2500 2.2 ghz fractional-n frequency synthesizer - 11 - philsar semiconductor inc. 146 colonnade road s. nepean, ontario, canada k2e 7y1 tel: 613-274-0922 fax: 613-274-0915 www.philsar.com pmp-001-ds2 v1.2 a shortened serial interface write where /cs is from 2 to 12 clock cycles wide and modulation data (2 to 12 bits) is presented on the mod_in pin. the mod_in is the alternate pin for entering modulation data directly in modulation data register with shortened /cs strobes. this mode is selected through the modulation control register . this method of data entry also eliminates the register address overhead on the serial interface and permits a different device than the one controlling the channel selection to enter the modulation data (eg. a microcontroller for channel selection and a dsp for modulation data). all serial interface bits are re-synchronized internally at the reference oscillator frequency and the content of the modulation data register is passed to the modulation unit at the next falling edge of the divided main vco frequency (f pd_main ). modulation data samples in the modulation data register can be from 2 to 12 bits long, enabling the user to select how many distinct frequency steps will be used for the desired modulation scheme. the user can also control the frequency deviation through the modulation data magnitude offset in the modulation control register . this permits shifting of the modulation data to accomplish a 2 m multiplication of frequency deviation 1 . 1. the programmable range of -0.5 to +0.5 of the main ds modulator can be exceeded up to the condition where the sum of the dividend and the modulation data obey -0.5625 ( n mod + dividend ) +0.5625 before requiring changing n integer .
PS2500 2.2 ghz fractional-n frequency synthesizer - 12 - philsar semiconductor inc. 146 colonnade road s. nepean, ontario, canada k2e 7y1 tel: 613-274-0922 fax: 613-274-0915 www.philsar.com pmp-001-ds2 v1.2 figure 3: PS2500 pinout /f vco_aux gnd cp_aux cp out_aux vcc cp_aux clock mod_in mux_out data xtal in /osc gnd xtal vcc xtal xtal out /nc ld/ps aux cp out_main vcc ecl/cml /cs gnd digital vcc digital gnd e cl/cml vcc ecl/cml f vco_aux vsub digital f vco_main gnd cp_main xtal acgnd / osc /f vco_main ld/ps main vcc cp_main 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
PS2500 2.2 ghz fractional-n frequency synthesizer - 13 - philsar semiconductor inc. 146 colonnade road s. nepean, ontario, canada k2e 7y1 tel: 613-274-0922 fax: 613-274-0915 www.philsar.com pmp-001-ds2 v1.2 table 1: ps1200 pin description pin label pin # type description clock pin 1 digital input clock signal pin. when /cs is low, the register address and data is shifted in address bits first on the data pin on the rising edge of clock . for more information, see ? serial interface ? on page5. data pin 27 digital input serial address and data input pin. address bits are followed by data bits. for more information, see ? serial interface ? on page5. /cs pin 28 digital input active low enable pin. enables loading of address and data on the data pin on the rising edge of clock. when /cs goes high, data is transferred to the register indicated by the address. subsequent clock edges are ignored. for more information, see ? serial interface ? on page5. mod_in pin 2 digital input alternate serial modulation data input pin. address bits are followed by data bits. mux_out pin 3 digital output internal multiplexer output. selects from oscillator frequency, main or auxiliary reference frequency, main or auxiliary divided vco frequency, serial data out or testability signals. this pin can be tri-stated from the general synthesizer registers. for more information, see ? general synthesizer registers ? on page22. xtal acgnd / osc pin 13 ground/input reference crystal ac ground, or external oscillator complementary input. xtal in /osc pin 14 input reference crystal input, or external oscillator differential input. xtal out /nc pin 15 input reference crystal output, or no connect. f vco_main pin 7 input main vco differential input. /f vco_main pin 8 input main vco complimentary differential input f vco_aux pin 23 input auxiliary vco differential input /f vco_aux pin 22 input auxiliary vco complimentary differential input cp out_main pin 11 analog output main charge pump output. the gain of the main charge pump phase detector can be controlled from the general synthesizer registers. ld/ps main pin 9 analog output programmable output pin. indicates main phase detector out-of-lock as an active low pulsing open collector output (high i mpedance when lock is detected), o r assists the loop filter in steering the main vco. this pin is configured from the general synthesizer registers.
PS2500 2.2 ghz fractional-n frequency synthesizer - 14 - philsar semiconductor inc. 146 colonnade road s. nepean, ontario, canada k2e 7y1 tel: 613-274-0922 fax: 613-274-0915 www.philsar.com pmp-001-ds2 v1.2 note: associated pairs of power and ground pins need to be decoupled using 0.1 m f capacitors. note: the PS2500 is supplied in an exposed pad 28-pin tssop package (ep-tssop). the exposed pad is located on the bottom side of the package, and must be connected to ground for proper operation. the exposed pad should be soldered directly to the circuit board. cp out_aux pin 20 analog output auxiliary charge pump output. the gain of the auxiliary charge pump phase detector can be controlled from the general synthesizer registers. ld/ps aux pin 18 analog output programmable output pin. indicates auxiliary phase detector out-of-lock as an active low pulsing open collector output (high impedance when lock is detected), or assists the loop filter in steering the auxiliary vco. this pin is configured from the general synthesizer registers. vcc digital pin 26 power and ground digital 3 volts. gnd digital pin 25 power and ground digital ground. vcc xtal pin 16 power and ground crystal oscillator ecl/cml 3 volts. gnd xtal pin 17 power and ground crystal oscillator ground. vcc ecl/cml pins 6, 24 power and ground ecl/cml 3 volt. removing power safely powers down the associated divider chain and charge pump. gnd ecl/cml pin 5 power and ground ecl/cml ground. vcc cp_main , vcc cp_aux pins 10, 19 power and ground main and auxiliary charge pump 3 to 5 volt. removing power safely powers down the associated divider chain and charge pump. gnd cp_main , gnd cp_aux pin 26 power and ground main and auxiliary charge pump ground. vsub digital pin 4 - substrate isolation, connect to ground pin label pin # type description
PS2500 2.2 ghz fractional-n frequency synthesizer - 15 - philsar semiconductor inc. 146 colonnade road s. nepean, ontario, canada k2e 7y1 tel: 613-274-0922 fax: 613-274-0915 www.philsar.com pmp-001-ds2 v1.2 absolute maximum ratings recommended operating conditions electrical characteristics maximum analog supply voltage: 3.6 vdc maximum digital supply voltage: 3.6 vdc maximum charge pump supply voltage: 5.25 vdc storage temperature: -65 c to + 150 c operating temperature: -40 c to + 85 c analog supplies: +2.7 to +3.3 vdc digital supply: +2.7 to +3.3 vdc charge pump supplies +2.7 to +5.0 vdc operating temperature (t a ): -40 c to + 85 c test conditions (unless otherwise stated) analog supplies: 3.0 vdc digital supply: 3.0 vdc charge pump supplies 3.0 vdc temperature (t a ): -40 c to + 85 c table 2: power consumption symbol parameter conditions min. typ. max. units p total total power consumption charge pump currents of 200 m a both synthesizers fractional f ref_main = 20 mhz f ref_aux = 1 mhz - 37.5 - mw i cc-pwdn power down current - - 10 - m a
PS2500 2.2 ghz fractional-n frequency synthesizer - 16 - philsar semiconductor inc. 146 colonnade road s. nepean, ontario, canada k2e 7y1 tel: 613-274-0922 fax: 613-274-0915 www.philsar.com pmp-001-ds2 v1.2 table 3: reference oscillator symbol parameter conditions min. typ. max. units f osc reference oscillator frequency - - - 50 mhz v osc oscillator sensitivity (as a buffer) ac coupled, single-ended 0.05 - 2.0 v pp f shift_ship frequency shift at shipping t = 25 c, v xtal = 3.0 v with 1% tolerance 20 pf crystal loading capacitors - - 3 ppm f shift_temp frequency shift vs temperature -40 c < t < +85 c v xtal = 3.0 v - - 3 f shift_supply frequency shift vs supply voltage t = 25 c 2.7 v v xtal 3.3 v - - 0.3 table 4: vcos symbol parameter conditions min. typ. max. units f vco_main main synthesizer operating frequency sinusoidal 300 a a. when operating in integer mode, minimum main synthesizer frequency is 100 mhz - 2200 mhz f vco_aux auxiliary synthesizer operating frequency 300 b b. when operating in integer mode, minimum auxiliary synthesizer frequency is 100 mhz - 500 v vco rf input sensitivity ac coupled 50 - 250 mv peak z vco_in rf input impedance - 1000 - w d f step_main main fractional-n tuning step size - f ref_main / 2 18 or f ref_main / 2 10 hz d f step_aux aux fractional-n tuning step size - f ref_aux / 2 10 table 5: noise symbol parameter conditions min. typ. max. units p nf phase noise floor in pll loop bandwidth - -132 + 20log(n) - dbc/hz p ib total spurious power - -70 - dbc
PS2500 2.2 ghz fractional-n frequency synthesizer - 17 - philsar semiconductor inc. 146 colonnade road s. nepean, ontario, canada k2e 7y1 tel: 613-274-0922 fax: 613-274-0915 www.philsar.com pmp-001-ds2 v1.2 table 6: phase detectors and charge pumps symbol parameter conditions min. typ. max. units f ref_main main phase detector frequency - - 25 mhz f ref_aux auxiliary phase detector frequency i cp-source charge pump output source current v cp = 0.5vcc cp 125 - 1000 m a i cp-sink charge pump output sink current -125 - -1000 i cp-accuracy - - - +/- 20 - % i cp vs. v cp charge pump output voltage linearity range 0.5v v cp ( vcc cp - 0.5v) t = 25 c gnd + 400 - vcc cp - 400 mv i cp vs. t charge pump current vs. temperature v cp = 0.5vcc cp -40 c < t < +85 c - - 5 % i cp vs. v cp charge pump current vs. voltage 0.5v v cp ( vcc cp - 0.5v) t = 25 c - - 8
PS2500 2.2 ghz fractional-n frequency synthesizer - 18 - philsar semiconductor inc. 146 colonnade road s. nepean, ontario, canada k2e 7y1 tel: 613-274-0922 fax: 613-274-0915 www.philsar.com pmp-001-ds2 v1.2 timing table 7: digital pins symbol parameter conditions min. typ. max. units v ih high level input voltage - 0.7v digital - - v v il low level input voltage - - - 0.3v digital v oh high level output voltage i oh = -2 ma v digital - 0.2 - - v ol low level output voltage i ol = 2 ma - - gnd + 0.2 table 8: timing ? serial interface symbol parameter conditions min. typ. max. units f clock clock frequency - - - 100 mhz t su data and /cs set up time to clock rising - 3 - - ns t hold data and /cs hold time after clock rising - 0 - - ns
PS2500 2.2 ghz fractional-n frequency synthesizer - 19 - philsar semiconductor inc. 146 colonnade road s. nepean, ontario, canada k2e 7y1 tel: 613-274-0922 fax: 613-274-0915 www.philsar.com pmp-001-ds2 v1.2 registers this section describes the PS2500?s registers. all register writes are programmed address first, followed directly with data. msbs are entered first. on power up, all register are reset to zero. register map register descriptions for more information on register loading order, see ? register loading order ? on page9. main synthesizer registers figure 4: hex0 main divider register (write only) table 9: PS2500 register map address register a a. all registers are write-only. length (with address bits) h0 main divider register 16 bits h1 main dividend msb register 16 bits h2 main dividend lsb register 16 bits h3 aux divider register 16 bits h4 aux dividend register 16 bits h5 reference frequency dividers register 16 bits h6 control register - phase detector/charge pumps 16 bits h7 control register - power down/multiplexer output select 16 bits h8 modulation control register 16 bits h9 modulation data register 16 bits modulation data register b - direct input b. no address bits are required for modulation data. any serial data between 2 and 12 bits long is considered modulation data. 2 length 12 bits main synthesizer divider index a3 0 1 2 3 4 5 6 7 8 9 10 11 0 a0 a1 a2 0 0 0 x x x
PS2500 2.2 ghz fractional-n frequency synthesizer - 20 - philsar semiconductor inc. 146 colonnade road s. nepean, ontario, canada k2e 7y1 tel: 613-274-0922 fax: 613-274-0915 www.philsar.com pmp-001-ds2 v1.2 this register contains the integer portion closest to the desired fractional-n (or the integer-n) value minus 32 for the main synthesizer. this register, in conjunction with the main dividend registers (which controls the fraction offset from -0.5 to +0.5), permits selection of a precise frequency. values to be loaded are: ? main synthesizer divider index = 9-bit value for the integer portion of the main synthesizer dividers. valid values for this register are from 6 to 505 (fractional-n) or from 0 to 511 (integer-n). figure 5: hex1 main dividend msb register (write only) figure 6: hex2 main dividend lsb register (write only) these registers control the fraction part of the desired fractional-n value and permit an offset of - 0.5 to + 0.5 to the main integer selected through the main divider register. values to be loaded are: ? main synthesizer dividend (msbs) = 10-bit value for the msbs of the 18-bit dividend for the main synthesizer. ? main synthesizer dividend (lsbs) = 8-bit value for the lsbs of the 18-bit dividend for the main synthesizer. note: when in 10-bit mode, the main synthesizer dividend (lsbs) is not required. for information on programming these registers, see ? synthesizer register programming ? on page6. for information on loading order for these registers, see ? register loading order ? on page9. main synthesizer dividend (msbs) a3 0 1 2 3 4 5 6 7 8 9 10 11 0 a0 a1 a2 0 0 1 x x main synthesizer dividend (lsbs) a3 0 1 2 3 4 5 6 7 8 9 10 11 0 a0 a1 a2 0 1 0 x x x x
PS2500 2.2 ghz fractional-n frequency synthesizer - 21 - philsar semiconductor inc. 146 colonnade road s. nepean, ontario, canada k2e 7y1 tel: 613-274-0922 fax: 613-274-0915 www.philsar.com pmp-001-ds2 v1.2 auxiliary synthesizer registers figure 7: hex3 auxiliary divider register (write only) this register contains the integer portion closest to the desired fractional-n (or integer-n) value minus 32 for the auxiliary synthesizer. this register, in conjunction with the auxiliary dividend register, which controls the fraction offset (from - 0.5 to + 0.5) permits selection of a precise frequency. values to be loaded are: ? auxiliary synthesizer divider index = 9-bit value for the integer portion of the auxiliary synthesizer dividers. valid values for this register are from 6 to 505 (fractional-n) or from 0 to 511 (integer-n). figure 8: hex4 auxiliary dividend register (write only) this register controls the fraction part of the desired fractional-n value and permits an offset of - 0.5 to + 0.5 to the auxiliary integer selected through the auxiliary divider register. values to be loaded are: ? auxiliary synthesizer dividend = 10-bit value for the dividend for the auxiliary synthesizer. for information on programming these registers, see ? synthesizer register programming ? on page6. for information on loading order for these registers, see ? register loading order ? on page9. auxiliary synthesizer divider index a3 0 1 2 3 4 5 6 7 8 9 10 11 0 a0 a1 a2 0 1 1 x x x auxiliary synthesizer dividend a3 0 1 2 3 4 5 6 7 8 9 10 11 0 a0 a1 a2 1 0 0 x x
PS2500 2.2 ghz fractional-n frequency synthesizer - 22 - philsar semiconductor inc. 146 colonnade road s. nepean, ontario, canada k2e 7y1 tel: 613-274-0922 fax: 613-274-0915 www.philsar.com pmp-001-ds2 v1.2 general synthesizer registers figure 9: hex5 reference frequency dividers register (write only) this register configures the dual-programmable reference frequency dividers for the main and auxiliary synthesizers. the dual-programmable reference frequency dividers provide the reference frequencies to the phase detectors by dividing the crystal oscillator frequency. the lower five bits hold the reference frequency divide index for the main phase detector. the next five bits hold the reference frequency divide index for the auxiliary phase detector. divide ratios from 1 to 32 are possible for each reference frequency divider. values to be loaded are: ? main reference frequency divider index = desired main oscillator frequency division ratio - 1. default value on power up is 0, signifying that the reference frequency is not divided for the main phase detector. ? auxiliary reference frequency divider index = desired auxiliary oscillator frequency division ratio - 1. default value on power up is 0, signifying that the reference frequency is not divided for the auxiliary phase detector. figure 10: hex6 phase detectors register (write only) this register permits control of the gain for both phase detectors, and configuration of the ld/ps pins for frequency power steering or lock detection. main reference frequency divider index a3 0 1 2 3 4 5 6 7 8 9 10 11 0 a0 a1 a2 1 0 1 x x auxiliary reference frequency divider index main phase detector gain main power steering/lock detect enable a3 0 1 2 3 4 5 6 7 8 9 10 11 0 a0 a1 a2 1 1 0 auxiliary phase detector gain auxiliary power steering/lock detect enable
PS2500 2.2 ghz fractional-n frequency synthesizer - 23 - philsar semiconductor inc. 146 colonnade road s. nepean, ontario, canada k2e 7y1 tel: 613-274-0922 fax: 613-274-0915 www.philsar.com pmp-001-ds2 v1.2 values to be loaded are: ? main phase detector gain = 5-bit value for programmable main phase detector gain, kd, of 20 to 160 m a/radian in steps of approximately 5 m a/radian. valid range is from 4 to 31 decimal for 20 to 160 m a/radian respectively. ? main power steering enable = 1-bit value to enable the frequency power steering circuitry of the main phase detector. when this bit is a 0, the ld/ps main is configured to be a lock detect active low open collector pin. when this bit is a 1, the ld/ps main is configured to be a frequency power steering pin and can be used to bypass the external main loop filter to provide faster frequency acquisition. ? aux phase detector gain = 5-bit value for programmable auxiliary phase detector gain, kd, of 20 to 160 m a/radian in steps of approximately 5 m a/radian. valid range is from 4 to 31 decimal for 20 to 160 m a/radian respectively. ? aux power steering enable = 1-bit value to enable the frequency power steering circuitry of the auxiliary phase detector. when this bit is a 0, the ld/ps aux is configured to be a lock detect active low open collector pin. when this bit is a 1, the ld/ps aux is configured to be a frequency power steering pin and may be used to bypass the external auxiliary loop filter to provide faster frequency acquisition. figure 11: hex7 power down and multiplexer output register (write only) this register permits control of the power-down modes, internal multiplexer output and main ds synthesizer fractionality. values to be loaded are: ? full power down = 1-bit value for powering down the whole chip except for the reference oscillator and the serial interface. when this bit is 0, the PS2500 is powered up. when this bit is 1, the PS2500 is in full power-down mode excluding the mux_out pin. full power down main synthesizer power down a3 0 1 2 3 4 5 6 7 8 9 10 11 0 a0 a1 a2 1 1 1 x x main synthesizer mode main synthesizer ds fractionality auxiliary synthesizer power down multiplexer output selection auxiliary synthesizer mode mu x_ou t pin tri-state enable
PS2500 2.2 ghz fractional-n frequency synthesizer - 24 - philsar semiconductor inc. 146 colonnade road s. nepean, ontario, canada k2e 7y1 tel: 613-274-0922 fax: 613-274-0915 www.philsar.com pmp-001-ds2 v1.2 ? main synthesizer power down = 1-bit value for powering down the main synthesizer. when this bit is 0, the main synthesizer is powered up. when this bit is 1, the main synthesizer is in power down mode. ? main synthesizer mode = 1-bit value for powering down the main synthesizer?s ds modulator and fractional unit to operate as a integer-n synthesizer. when this bit is 0, the main synthesizer is in fractional-n mode. when this bit is 1, the main synthesizer is in integer-n mode. ? main synthesizer ds fractionality = 1-bit value to configure the size of the main ds modulator. this has a direct effect on power consumption and on the level of fractionality and step size. when this bit is 0, the main ds modulator is 18-bit with fractionality of 2 18 and step size of f ref_main /262144. when this bit is 1, the main ds modulator is 10-bit with fractionality of 2 10 and step size of f ref_main /1024. ? auxiliary synthesizer power down = 1-bit value for powering down the auxiliary synthesizer. when this bit is 0, the auxiliary synthesizer is powered up. when this bit is 1, the auxiliary synthesizer is in power-down mode. ? auxiliary synthesizer mode = 1-bit value for powering down the auxiliary synthesizer?s ds modulator and fractional unit to operate as a integer-n synthesizer. when this bit is 0, the auxiliary synthesizer is in fractional-n mode. when this bit is 1, the auxiliary synthesizer is in integer-n mode. note: there are no special power up sequences required for the PS2500. ? multiplexer output selection = 3-bit value for selecting which internal signal is output to the mux_out pin. internal signals available on this pin are: ? reference oscillator: f ref ? main or auxiliary divided reference (post reference frequency main or auxiliary dividers): f ref_main or f ref_aux ? main or auxiliary phase detector frequency (post main and auxiliary frequency dividers): f pd_main or f pd_aux ? serial data out, for loop-back and test purposes refer to the following table for more information. table 10: multiplexer output multiplexer output select bit 2 multiplexer output select bit 1 multiplexer output select bit 0 multiplexer output (mux_out) 0 0 0 reference oscillator 0 0 1 auxiliary reference frequency (f ref_aux ) 0 1 0 main reference frequency (f ref_main ) 0 1 1 auxiliary phase detector frequency (f pd_aux ) 1 0 0 main phase detector frequency (f pd_main ) 1 0 1 serial data out 1 1 0 serial interface register test output
PS2500 2.2 ghz fractional-n frequency synthesizer - 25 - philsar semiconductor inc. 146 colonnade road s. nepean, ontario, canada k2e 7y1 tel: 613-274-0922 fax: 613-274-0915 www.philsar.com pmp-001-ds2 v1.2 ? mux_out pin tri-state enable = 1-bit value for tri-stating the mux_out pin. when this bit is 0, the mux_out pin is enabled. when this bit is 1, the mux_out pin is tri-stated. figure 12: hex8 modulation control register (write only) this register is used to configure the modulation unit of the main synthesizer. the modulation unit provides for adding or subtracting a frequency offset to the selected center frequency at which the main synthesizer is operating. the size of the modulation data sample, controlled by the duration of /cs , can be from 2 to 12 bits wide, to provide from 4 to 4096 selectable frequency offsets steps. the modulation data magnitude offset selects the magnitude multiplier for the modulation data and can be from 0 to 8. values to be loaded are: modulation data magnitude offset = 4-bit value indicating magnitude multiplier (m) for the modulation data samples. valid values range from 0 to 13, effectively providing a 2 m multiplication of the modulation data sample. modulation data input select = 1-bit value indicating the pin on which modulation data samples are serially input when /cs is between 2 and 12 bits long. when this bit is 0, modulation data samples are to be presented on the data pin. when this bit is 1, modulation data samples are to be presented on the mod_in pin. for more details, please refer to section ? direct digital modulation ? on page10. modulation address disable = 1-bit value indicating the presence of the address as modulation data samples are presented on either the mod_in or data pins. when this bit is 0, address is presented with the modulation data samples (i.e. all transfers are 16 bits long). when this bit is 1, no address is presented with the modulation data samples (i.e. all transfers are 2 to 12 bits long). for more details, please refer to section ? direct digital modulation ? on page10. reserved b its modulation data magnitude offset a3 0 1 2 3 4 5 6 7 8 9 10 11 0 0 0 0 1 a0 a1 a2 0 0 0 x x modulation data input select modulation address disable
PS2500 2.2 ghz fractional-n frequency synthesizer - 26 - philsar semiconductor inc. 146 colonnade road s. nepean, ontario, canada k2e 7y1 tel: 613-274-0922 fax: 613-274-0915 www.philsar.com pmp-001-ds2 v1.2 figure 13: hex9 modulation data register (write only) this register is used to load the modulation data samples to the modulation unit. this value is transferred to the modulation unit on the falling edge of f pd_main where it will be passed to the main ds modulator at the selected magnitude offset on the next falling edge of f pd_main . values to be loaded are: modulation data bits = modulation data samples representing desired instantaneous frequency offset to the selected main synthesizer frequency (selected channel) before being affected by the modulation data magnitude offset . modulation data bits a3 0 1 2 3 4 5 6 7 8 9 10 11 1 a0 a1 a2 0 0 1
PS2500 2.2 ghz fractional-n frequency synthesizer - 27 - philsar semiconductor inc. 146 colonnade road s. nepean, ontario, canada k2e 7y1 tel: 613-274-0922 fax: 613-274-0915 www.philsar.com pmp-001-ds2 v1.2 packaging information figure 14: 28-pin ep-tssop table 11: 28-pin ep-tssop dimensions all dimensions in millimeters (mm) min max a 1.10 a 1 0.05 0.15 a 2 0.85 0.95 d 9.70 bsc e 6.40 bsc e 1 4.30 4.50 l 0.50 0.70 p 3.5 p 1 3.0 e 0.65 bsc b 0.19 0.30 top view e e 1 d b e 1 top view e e 1 d b e 1 e e 1 e e 1 e 1 d d b e 1 exposed pad bottom view p p 1 exposed pad bottom view p p 1 p p 1 a a 2 a 1 l side view detail a a 2 a 1 l a a 2 a 1 l side view detail
PS2500 2.2 ghz fractional-n frequency synthesizer - 28 - philsar semiconductor inc. 146 colonnade road s. nepean, ontario, canada k2e 7y1 tel: 613-274-0922 fax: 613-274-0915 www.philsar.com pmp-001-ds2 v1.2 ordering information table 12: ordering information electrostatic discharge information the PS2500 device is an electrostatic sensitive device. observe precautions when handling. part number temperature range package minimum order quantity notes PS2500ait-es2/2 - 28-pin tssop 2 engineering prototype units that are not necessarily representative of the final device?s electrical specifications. verified for functionality only, quality and reliability verification not completed. PS2500ait -40 to 85c 28-pin tssop 50

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